Connectivity Systems Engineer
Apple
Emeryville, CA · Onsite · Full Time
Posted
Job description
Come join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will help de-risk our silicon well ahead of tape-out by owning the pre-silicon emulation environment that enables the team to exercise and verify new designs early and with confidence. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. Description This role is central to Apple's pre-silicon verification effort for wireless SoCs, centered on the Palladium emulation platform. You will be the first to bring up each newly released emulation build, and you will design and own the framework and infrastructure - register maps, initialization and boot sequences, clock and reset, and system-level configuration - that brings the emulated SoC into an operational state and enables the wider team to run their own design verification. Working at the intersection of digital design, firmware, and validation, you will own and evolve this infrastructure across successive silicon generations, while also contributing to pre-silicon emulation and lab bring-up of Bluetooth and UWB silicon. Responsibilities: Act as the initial validation point for each released Palladium emulation build, performing early smoke and sanity testing to confirm the build is functional, correctly configured, and ready for broader team use. Build and own the framework and infrastructure that exercises the Palladium build - including register map definitions, initialization and boot sequences, clock and reset setup, and other system-level configuration - to bring the emulated SoC into an operational state. Abstract platform bring-up and configuration complexity into reusable infrastructure and tooling, enabling the rest of the team to concentrate on their own design verification rather than platform-level setup.…