Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer (f/m/d)

Job description

About us We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects About our technology The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution The Role We are seeking an experienced Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer to take technical ownership of the complete tape-out flow — from GDS database integration and mask data preparation through mask release, first silicon bring-up, and post-tapeout support. In this role, you will drive EIC+PIC DfX co-integration (Design for Functionality, Manufacturing, Test, Packaging, and Reliability) across a 300 mm graphene photonics platform, ensuring seamless alignment between design, fabrication, testing, and packaging requirements throughout the development cycle. To join our team, you should be excited to: Own the complete tape-out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, and rule file maintenance for PIC-EIC integration and new process nodes. Lead GDS and reticle-to-fab delivery, formal mask release activities, and ensure all layers, formats, and data structures comply with fab specifications. Drive DFM and DFT integration through yield optimization, hotspot mitigation, layout optimization, and implementation of scan chains, test pads, and optical probe structures…