Senior Physical Design Engineer

Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! We have an exciting opportunity for a talented Senior Physical Design Engineer to join our growing team in Edinburgh. In this role, you will have the opportunity to implement industry leading mixed-signal SOCs for consumer markets and become part of an organisation operating at the forefront of cutting-edge technology. This role would suit a candidate with an ability to work independently and as part of a wider design team. Responsibilities: All aspects of RTL to GDS2 physical implementation for complex ASIC projects. Working with Digital Design, Analogue Layout and DFT teams to ensure on time and high-quality results. Participating in project scoping and planning activities. Developing P&R methodologies for continuous improvement. Required Skills and Qualifications: Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a Physical Design position. Wide experience with industry standard EDA tools for digital implementation and signoff, and the ideal candidate should be familiar with: Synopsys Design Compiler and Primetime Cadence Innovus, Voltus and Conformal Hands-on working knowledge of deep sub-micron ASIC implementation and expertise in areas such as: RTL synthesis Timing constraint debug and development Floorplanning and power planning Clock tree synthesis P&R optimisation, timing closure and ECO implementation Static timing analysis Logical Equivalence Checks Power and EMIR analysis Proven responsibility for full design flow to design closure and tapeout. Knowledge of automating and advancing flows with proficiency in scripting. Ability to perform debug and analysis of designs, libraries, and technology files. Good communication and excellent collaboration skills. This position is…